br_mis_pred
br_mis_pred_retired
br_pred
br_retired
bus_access
bus_cycles
cid_write_retired
cpu_cycles
exc_return
exc_taken
inst_retired
inst_spec
l1d_cache
l1d_cache_refill
l1d_cache_wb
l1d_tlb
l1d_tlb_refill
l1i_cache
l1i_cache_refill
l1i_tlb
l1i_tlb_refill
l2d_cache
l2d_cache_allocate
l2d_cache_refill
l2d_cache_wb
l2d_tlb
l2d_tlb_refill
l3d_cache
l3d_cache_allocate
l3d_cache_refill
l3d_cache_wb
mem_access
memory_error
sample_collision
sample_feed
sample_filtrate
sample_pop
stall_backend
stall_frontend
ttbr_write_retired